/*
 * Copyright (c) Huawei Technologies Co., Ltd. 2019-2022. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * Description:
 * Author: huawei
 * Create: 2019-10-15
 */

#ifndef IO_SUBCTRL_REG_OFFSET_H
#define IO_SUBCTRL_REG_OFFSET_H

/* IO_SUBCTRL Base address of Module's Register */
#define IO_SUBCTRL_BASE                       (0)

/* IO_SUBCTRL Registers' Definitions */
#define IO_SUBCTRL_SC_SMMU_ICG_EN_REG                   (IO_SUBCTRL_BASE + 0x300)  /* SMMU CLK EN */
#define IO_SUBCTRL_SC_SMMU_ICG_DIS_REG                  (IO_SUBCTRL_BASE + 0x304)  /* SMMU CLK DISEN */
#define IO_SUBCTRL_SC_GPIO_ICG_EN_REG                   (IO_SUBCTRL_BASE + 0x308)  /* GPIO CLK EN */
#define IO_SUBCTRL_SC_GPIO_ICG_DIS_REG                  (IO_SUBCTRL_BASE + 0x30C)  /* GPIO CLK DISEN */
#define IO_SUBCTRL_SC_APB_IO_MUX_ICG_EN_REG             (IO_SUBCTRL_BASE + 0x310)  /* APB_IO_MUX CLK EN */
#define IO_SUBCTRL_SC_APB_IO_MUX_ICG_DIS_REG            (IO_SUBCTRL_BASE + 0x314)  /* APB_IO_MUX CLK DISEN */
#define IO_SUBCTRL_SC_PROBE_ICG_EN_REG                  (IO_SUBCTRL_BASE + 0x318)  /* PROBE CLK EN */
#define IO_SUBCTRL_SC_PROBE_ICG_DIS_REG                 (IO_SUBCTRL_BASE + 0x31C)  /* PROBE CLK DISEN */
#define IO_SUBCTRL_SC_MDIO_ICG_EN_REG                   (IO_SUBCTRL_BASE + 0x320)  /* MDIO CLK EN */
#define IO_SUBCTRL_SC_MDIO_ICG_DIS_REG                  (IO_SUBCTRL_BASE + 0x324)  /* MDIO CLK DISEN */
#define IO_SUBCTRL_SC_HILINK0_ICG_EN_REG                (IO_SUBCTRL_BASE + 0x328)  /* HILINK0 CLK EN */
#define IO_SUBCTRL_SC_HILINK0_ICG_DIS_REG               (IO_SUBCTRL_BASE + 0x32C)  /* HILINK0 CLK DISEN */
#define IO_SUBCTRL_SC_HILINK1_ICG_EN_REG                (IO_SUBCTRL_BASE + 0x330)  /* HILINK1 CLK EN */
#define IO_SUBCTRL_SC_HILINK1_ICG_DIS_REG               (IO_SUBCTRL_BASE + 0x334)  /* HILINK1 CLK DISEN */
#define IO_SUBCTRL_SC_SDS_ICG_EN_REG                    (IO_SUBCTRL_BASE + 0x338)  /* SDS CLK EN */
#define IO_SUBCTRL_SC_SDS_ICG_DIS_REG                   (IO_SUBCTRL_BASE + 0x33C)  /* SDS CLK DISEN */
#define IO_SUBCTRL_SC_PCIE_BRG_ICG_EN_REG               (IO_SUBCTRL_BASE + 0x340)  /* PCIE_BRG CLK EN */
#define IO_SUBCTRL_SC_PCIE_BRG_ICG_DIS_REG              (IO_SUBCTRL_BASE + 0x344)  /* PCIE_BRG CLK DISEN */
#define IO_SUBCTRL_SC_PCIE0_CTRL0_ICG_EN_REG            (IO_SUBCTRL_BASE + 0x348)  /* PCIE_CTRL0 CLK EN */
#define IO_SUBCTRL_SC_PCIE0_CTRL0_ICG_DIS_REG           (IO_SUBCTRL_BASE + 0x34C)  /* PCIE_CTRL0 CLK DISEN */
#define IO_SUBCTRL_SC_PCIE0_CTRL1_ICG_EN_REG            (IO_SUBCTRL_BASE + 0x350)  /* PCIE0_CTRL1 CLK EN */
#define IO_SUBCTRL_SC_PCIE0_CTRL1_ICG_DIS_REG           (IO_SUBCTRL_BASE + 0x354)  /* PCIE0_CTRL1 CLK DISEN */
#define IO_SUBCTRL_SC_PCIE1_CTRL0_ICG_EN_REG            (IO_SUBCTRL_BASE + 0x358)  /* PCIE1_CTRL0 CLK EN */
#define IO_SUBCTRL_SC_PCIE1_CTRL0_ICG_DIS_REG           (IO_SUBCTRL_BASE + 0x35C)  /* PCIE1_CTRL0 CLK DISEN */
#define IO_SUBCTRL_SC_PCIE1_CTRL1_ICG_EN_REG            (IO_SUBCTRL_BASE + 0x360)  /* PCIE1_CTRL1 CLK EN */
#define IO_SUBCTRL_SC_PCIE1_CTRL1_ICG_DIS_REG           (IO_SUBCTRL_BASE + 0x364)  /* PCIE1_CTRL1 CLK DISEN */
#define IO_SUBCTRL_SC_PCIE2_CTRL0_ICG_EN_REG            (IO_SUBCTRL_BASE + 0x368)  /* PCIE2_CTRL0 CLK EN */
#define IO_SUBCTRL_SC_PCIE2_CTRL0_ICG_DIS_REG           (IO_SUBCTRL_BASE + 0x36C)  /* PCIE2_CTRL0 CLK DISEN */
#define IO_SUBCTRL_SC_PCIE2_CTRL1_ICG_EN_REG            (IO_SUBCTRL_BASE + 0x370)  /* PCIE2_CTRL1 CLK EN */
#define IO_SUBCTRL_SC_PCIE2_CTRL1_ICG_DIS_REG           (IO_SUBCTRL_BASE + 0x374)  /* PCIE2_CTRL1 CLK DISEN */
#define IO_SUBCTRL_SC_PCIE3_CTRL0_ICG_EN_REG            (IO_SUBCTRL_BASE + 0x378)  /* PCIE3_CTRL0 CLK EN */
#define IO_SUBCTRL_SC_PCIE3_CTRL0_ICG_DIS_REG           (IO_SUBCTRL_BASE + 0x37C)  /* PCIE3_CTRL0 CLK DISEN */
#define IO_SUBCTRL_SC_PCIE3_CTRL1_ICG_EN_REG            (IO_SUBCTRL_BASE + 0x380)  /* PCIE3_CTRL1 CLK EN */
#define IO_SUBCTRL_SC_PCIE3_CTRL1_ICG_DIS_REG           (IO_SUBCTRL_BASE + 0x384)  /* PCIE3_CTRL1 CLK DISEN */
#define IO_SUBCTRL_SC_USB_ICG_EN_REG                    (IO_SUBCTRL_BASE + 0x388)  /* USB CLK EN */
#define IO_SUBCTRL_SC_USB_ICG_DIS_REG                   (IO_SUBCTRL_BASE + 0x38C)  /* USB CLK DISEN */
#define IO_SUBCTRL_SC_SATA_ICG_EN_REG                   (IO_SUBCTRL_BASE + 0x390)  /* SATA CLK EN */
#define IO_SUBCTRL_SC_SATA_ICG_DIS_REG                  (IO_SUBCTRL_BASE + 0x394)  /* SATA CLK DISEN */
#define IO_SUBCTRL_SC_NIC_INTF0_ICG_EN_REG              (IO_SUBCTRL_BASE + 0x398)
#define IO_SUBCTRL_SC_NIC_INTF0_ICG_DIS_REG             (IO_SUBCTRL_BASE + 0x39C)
#define IO_SUBCTRL_SC_NIC_INTF1_ICG_EN_REG              (IO_SUBCTRL_BASE + 0x3A0)
#define IO_SUBCTRL_SC_NIC_INTF1_ICG_DIS_REG             (IO_SUBCTRL_BASE + 0x3A4)
#define IO_SUBCTRL_SC_RGMII_ICG_EN_REG                  (IO_SUBCTRL_BASE + 0x3A8)  /* RGMII CLK EN */
#define IO_SUBCTRL_SC_RGMII_ICG_DIS_REG                 (IO_SUBCTRL_BASE + 0x3AC)  /* RGMII CLK DISEN */
#define IO_SUBCTRL_SC_HPM_CLK_EN_REG                    (IO_SUBCTRL_BASE + 0x3B0)
#define IO_SUBCTRL_SC_HPM_CLK_DIS_REG                   (IO_SUBCTRL_BASE + 0x3B4)
#define IO_SUBCTRL_SC_TSENSOR_ICG_EN_REG                (IO_SUBCTRL_BASE + 0x3C0)  /* TSENSOR CLK EN */
#define IO_SUBCTRL_SC_TSENSOR_ICG_DIS_REG               (IO_SUBCTRL_BASE + 0x3C4)  /* TSENSOR CLK DISEN */
#define IO_SUBCTRL_SC_HILINK_SRAM_ICG_EN_REG            (IO_SUBCTRL_BASE + 0x3C8)  /* HILINK SRAM CLK EN */
#define IO_SUBCTRL_SC_HILINK_SRAM_ICG_DIS_REG           (IO_SUBCTRL_BASE + 0x3CC)  /* HILINK SRAM CLK DISEN */
#define IO_SUBCTRL_SC_BCBIST_ICG_EN_REG                 (IO_SUBCTRL_BASE + 0x3D0)  /* BCBIST CLK EN */
#define IO_SUBCTRL_SC_BCBIST_ICG_DIS_REG                (IO_SUBCTRL_BASE + 0x3D4)  /* BCBIST CLK DISEN */
#define IO_SUBCTRL_SC_GPIO_RESET_REQ_REG                (IO_SUBCTRL_BASE + 0x400)
#define IO_SUBCTRL_SC_GPIO_RESET_DREQ_REG               (IO_SUBCTRL_BASE + 0x404)
#define IO_SUBCTRL_SC_APB_IO_MUX_RESET_REQ_REG          (IO_SUBCTRL_BASE + 0x408)
#define IO_SUBCTRL_SC_APB_IO_MUX_RESET_DREQ_REG         (IO_SUBCTRL_BASE + 0x40C)
#define IO_SUBCTRL_SC_MDIO_RESET_REQ_REG                (IO_SUBCTRL_BASE + 0x418)
#define IO_SUBCTRL_SC_MDIO_RESET_DREQ_REG               (IO_SUBCTRL_BASE + 0x41C)
#define IO_SUBCTRL_SC_HILINK0_RESET_REQ_REG             (IO_SUBCTRL_BASE + 0x420)
#define IO_SUBCTRL_SC_HILINK0_RESET_DREQ_REG            (IO_SUBCTRL_BASE + 0x424)
#define IO_SUBCTRL_SC_HILINK1_RESET_REQ_REG             (IO_SUBCTRL_BASE + 0x428)
#define IO_SUBCTRL_SC_HILINK1_RESET_DREQ_REG            (IO_SUBCTRL_BASE + 0x42C)
#define IO_SUBCTRL_SC_SDS_RESET_REQ_REG                 (IO_SUBCTRL_BASE + 0x430)
#define IO_SUBCTRL_SC_SDS_RESET_DREQ_REG                (IO_SUBCTRL_BASE + 0x434)
#define IO_SUBCTRL_SC_USB_RESET_REQ_REG                 (IO_SUBCTRL_BASE + 0x438)
#define IO_SUBCTRL_SC_USB_RESET_DREQ_REG                (IO_SUBCTRL_BASE + 0x43C)
#define IO_SUBCTRL_SC_USBPHY_RESET_REQ_REG              (IO_SUBCTRL_BASE + 0x440)
#define IO_SUBCTRL_SC_USBPHY_RESET_DREQ_REG             (IO_SUBCTRL_BASE + 0x444)
#define IO_SUBCTRL_SC_SATA_RESET_REQ_REG                (IO_SUBCTRL_BASE + 0x448)
#define IO_SUBCTRL_SC_SATA_RESET_DREQ_REG               (IO_SUBCTRL_BASE + 0x44C)
#define IO_SUBCTRL_SC_NIC_INTF0_RESET_REQ_REG           (IO_SUBCTRL_BASE + 0x450)
#define IO_SUBCTRL_SC_NIC_INTF0_RESET_DREQ_REG          (IO_SUBCTRL_BASE + 0x454)
#define IO_SUBCTRL_SC_NIC_INTF1_RESET_REQ_REG           (IO_SUBCTRL_BASE + 0x458)
#define IO_SUBCTRL_SC_NIC_INTF1_RESET_DREQ_REG          (IO_SUBCTRL_BASE + 0x45C)
#define IO_SUBCTRL_SC_PCIE0_CTRL_RESET_REQ_REG          (IO_SUBCTRL_BASE + 0x460)
#define IO_SUBCTRL_SC_PCIE0_CTRL_RESET_DREQ_REG         (IO_SUBCTRL_BASE + 0x464)
#define IO_SUBCTRL_SC_PCIE1_CTRL_RESET_REQ_REG          (IO_SUBCTRL_BASE + 0x468)
#define IO_SUBCTRL_SC_PCIE1_CTRL_RESET_DREQ_REG         (IO_SUBCTRL_BASE + 0x46C)
#define IO_SUBCTRL_SC_PCIE2_CTRL_RESET_REQ_REG          (IO_SUBCTRL_BASE + 0x470)
#define IO_SUBCTRL_SC_PCIE2_CTRL_RESET_DREQ_REG         (IO_SUBCTRL_BASE + 0x474)
#define IO_SUBCTRL_SC_PCIE3_CTRL_RESET_REQ_REG          (IO_SUBCTRL_BASE + 0x478)
#define IO_SUBCTRL_SC_PCIE3_CTRL_RESET_DREQ_REG         (IO_SUBCTRL_BASE + 0x47C)
#define IO_SUBCTRL_SC_RGMII_RESET_REQ_REG               (IO_SUBCTRL_BASE + 0x480)
#define IO_SUBCTRL_SC_RGMII_RESET_DREQ_REG              (IO_SUBCTRL_BASE + 0x484)
#define IO_SUBCTRL_SC_HPM_RESET_REQ_REG                 (IO_SUBCTRL_BASE + 0x488)
#define IO_SUBCTRL_SC_HPM_RESET_DREQ_REG                (IO_SUBCTRL_BASE + 0x48C)
#define IO_SUBCTRL_SC_TSENSOR_RESET_REQ_REG             (IO_SUBCTRL_BASE + 0x4C0)
#define IO_SUBCTRL_SC_TSENSOR_RESET_DREQ_REG            (IO_SUBCTRL_BASE + 0x4C4)
#define IO_SUBCTRL_SC_BCBIST_RESET_REQ_REG              (IO_SUBCTRL_BASE + 0x4C8)
#define IO_SUBCTRL_SC_BCBIST_RESET_DREQ_REG             (IO_SUBCTRL_BASE + 0x4CC)
#define IO_SUBCTRL_SC_DCIP_BIST_CTRL0_REG               (IO_SUBCTRL_BASE + 0x1200)
/* DECODER access default space response error or not */
#define IO_SUBCTRL_SC_DISPATCH_ERRRSP_REG               (IO_SUBCTRL_BASE + 0x2000)
#define IO_SUBCTRL_SC_GPIO_SYN_EN_REG                   (IO_SUBCTRL_BASE + 0x2004) /* GPIO MODE SELECT */
#define IO_SUBCTRL_SC_SATA_SAFE_CTRL_REG                (IO_SUBCTRL_BASE + 0x2008)
/* temperature threshold config of on-chip temperature sensor */
#define IO_SUBCTRL_SC_TSENSOR_ALARM0_REG                (IO_SUBCTRL_BASE + 0x20C0)
/* ultrahigh temperature threshold config of on-chip temperature sensor */
#define IO_SUBCTRL_SC_TSENSOR_ALARM1_REG                (IO_SUBCTRL_BASE + 0x20C4)
/* temperature sensor timeout config */
#define IO_SUBCTRL_SC_TSENSOR_TIMEOUT_NUM_REG           (IO_SUBCTRL_BASE + 0x20C8)
/* hardware successively read temperature value and get average value setting reg（not allow setting value 0x0和0x1）*/
#define IO_SUBCTRL_SC_TSENSOR_SAMPLE_NUM_REG            (IO_SUBCTRL_BASE + 0x20CC)
/* on-chip temperature sensor working parameter config */
#define IO_SUBCTRL_SC_TSENSOR0_CTRL_REG                 (IO_SUBCTRL_BASE + 0x20D0)
/* temperature sensor soft/hard ware switch */
#define IO_SUBCTRL_SC_TSENSOR_MODE_SEL_REG              (IO_SUBCTRL_BASE + 0x20DC)
#define IO_SUBCTRL_SC_TSENSOR_SAMPLE_CTRL_REG           (IO_SUBCTRL_BASE + 0x20E0)
/* temperature sensor simulating IP's inner debug ctrl switch */
#define IO_SUBCTRL_SC_TEMP_DEBUG_REG                    (IO_SUBCTRL_BASE + 0x20E4)
 /* TSENSOR polling interval count configuration register */
#define IO_SUBCTRL_SC_TSENSOR_WAIT_CNT_REG              (IO_SUBCTRL_BASE + 0x20E8)
/* Tsensor hardware STATUS machine mode DFX */
#define IO_SUBCTRL_SC_TSENSOR_DFX_REG                   (IO_SUBCTRL_BASE + 0x20EC)
/* average temperature info form latched local sensor */
#define IO_SUBCTRL_TSENSOR_LOCAL_AVG_DATA_REG           (IO_SUBCTRL_BASE + 0x20F0)
/* average temperature info form latched remote sensor */
#define IO_SUBCTRL_TSENSOR_REMOTE0_AVG_DATA_REG         (IO_SUBCTRL_BASE + 0x20F4)
#define IO_SUBCTRL_SC_TSENSOR_LOOP_CTRL_REG             (IO_SUBCTRL_BASE + 0x20F8)
#define IO_SUBCTRL_SC_TSENSOR_TIMEOUT_CNT_CLR_REG       (IO_SUBCTRL_BASE + 0x20FC)
#define IO_SUBCTRL_SC_FUNC_MBIST_CLK_SEL_REG            (IO_SUBCTRL_BASE + 0x2208)
#define IO_SUBCTRL_PCIE_DAW0_ADDR_REG                   (IO_SUBCTRL_BASE + 0x2500)
#define IO_SUBCTRL_PCIE_DAW0_SIZE_ID_REG                (IO_SUBCTRL_BASE + 0x2504)
#define IO_SUBCTRL_PCIE_DAW1_ADDR_REG                   (IO_SUBCTRL_BASE + 0x2510)
#define IO_SUBCTRL_PCIE_DAW1_SIZE_ID_REG                (IO_SUBCTRL_BASE + 0x2514)
#define IO_SUBCTRL_PCIE_DAW2_ADDR_REG                   (IO_SUBCTRL_BASE + 0x2520)
#define IO_SUBCTRL_PCIE_DAW2_SIZE_ID_REG                (IO_SUBCTRL_BASE + 0x2524)
#define IO_SUBCTRL_PCIE_DAW3_ADDR_REG                   (IO_SUBCTRL_BASE + 0x2530)
#define IO_SUBCTRL_PCIE_DAW3_SIZE_ID_REG                (IO_SUBCTRL_BASE + 0x2534)
#define IO_SUBCTRL_PCIE_DAW4_ADDR_REG                   (IO_SUBCTRL_BASE + 0x2540)
#define IO_SUBCTRL_PCIE_DAW4_SIZE_ID_REG                (IO_SUBCTRL_BASE + 0x2544)
#define IO_SUBCTRL_PCIE_DAW5_ADDR_REG                   (IO_SUBCTRL_BASE + 0x2550)
#define IO_SUBCTRL_PCIE_DAW5_SIZE_ID_REG                (IO_SUBCTRL_BASE + 0x2554)
#define IO_SUBCTRL_PCIE_DAW6_ADDR_REG                   (IO_SUBCTRL_BASE + 0x2560)
#define IO_SUBCTRL_PCIE_DAW6_SIZE_ID_REG                (IO_SUBCTRL_BASE + 0x2564)
#define IO_SUBCTRL_PCIE_DAW7_ADDR_REG                   (IO_SUBCTRL_BASE + 0x2570)
#define IO_SUBCTRL_PCIE_DAW7_SIZE_ID_REG                (IO_SUBCTRL_BASE + 0x2574)
#define IO_SUBCTRL_SC_PCIE_DAW_EN_REG                   (IO_SUBCTRL_BASE + 0x2680)
#define IO_SUBCTRL_PCIE_WRAP_DECODER_ERR_INT_MASK_REG   (IO_SUBCTRL_BASE + 0x2700)
/* PCIE_WRAP decoder STATUS */
#define IO_SUBCTRL_PCIE_WRAP_DECODER_ERR_REG            (IO_SUBCTRL_BASE + 0x2800)
#define IO_SUBCTRL_SC_SEL_CLK_CORE_PCIE_REG             (IO_SUBCTRL_BASE + 0x2900)
#define IO_SUBCTRL_SC_HPM_EN_REG                        (IO_SUBCTRL_BASE + 0x2F00)
#define IO_SUBCTRL_SC_HPM_DIV_REG                       (IO_SUBCTRL_BASE + 0x2F04)
#define IO_SUBCTRL_HPM_PC_0_ORG_REG                     (IO_SUBCTRL_BASE + 0x2F08) /* hpm 0v STATUS */
#define IO_SUBCTRL_HPM_PC_1_ORG_REG                     (IO_SUBCTRL_BASE + 0x2F0C) /* hpm 0v STATUS */
#define IO_SUBCTRL_HPM_PC_VALID_REG                     (IO_SUBCTRL_BASE + 0x2F10) /* hpm valid STATUS */
#define IO_SUBCTRL_SC_TP_MEM_CTRL_REG                   (IO_SUBCTRL_BASE + 0x3200)
#define IO_SUBCTRL_SC_SP_MEM_CTRL_REG                   (IO_SUBCTRL_BASE + 0x3204)
#define IO_SUBCTRL_SC_MEM_POWER_MODE_REG                (IO_SUBCTRL_BASE + 0x3208)
#define IO_SUBCTRL_AUTOLF_FORCE_BUSY_REG                (IO_SUBCTRL_BASE + 0x3400)
#define IO_SUBCTRL_AUTOLF_FORCE_IDLE_REG                (IO_SUBCTRL_BASE + 0x3404)
#define IO_SUBCTRL_AUTOLF_IDLE_IN_TH_REG                (IO_SUBCTRL_BASE + 0x3408)
#define IO_SUBCTRL_AUTOLF_CFG_EN_REG                    (IO_SUBCTRL_BASE + 0x340C)
#define IO_SUBCTRL_AUTOLF_IDLE_STATUS_REG               (IO_SUBCTRL_BASE + 0x3410)
#define IO_SUBCTRL_AUTOLF_IDLE_CNT_REG                  (IO_SUBCTRL_BASE + 0x3414)
#define IO_SUBCTRL_SC_USBC_AHBS_BIGENDIAN_REG           (IO_SUBCTRL_BASE + 0x3500)
#define IO_SUBCTRL_SC_USBC_AXI_NS_REG                   (IO_SUBCTRL_BASE + 0x3504)
#define IO_SUBCTRL_SC_USBC_AXIM_BIGENDIAN_REG           (IO_SUBCTRL_BASE + 0x3508)
#define IO_SUBCTRL_SC_USBC_BME_REG                      (IO_SUBCTRL_BASE + 0x350C)
#define IO_SUBCTRL_SC_USBC_ERR_INJ_EN_REG               (IO_SUBCTRL_BASE + 0x3510)
#define IO_SUBCTRL_SC_USBC_MSI_EN_REG                   (IO_SUBCTRL_BASE + 0x3514)
#define IO_SUBCTRL_SC_USBC_U2_DISABLE_REG               (IO_SUBCTRL_BASE + 0x3518)
#define IO_SUBCTRL_SC_USBC_U3_DISABLE_REG               (IO_SUBCTRL_BASE + 0x351C)
#define IO_SUBCTRL_SC_USBC_UTMI8BIT_EN_REG              (IO_SUBCTRL_BASE + 0x3520)
#define IO_SUBCTRL_SC_USBC_UTMI_ULPI_SEL_REG            (IO_SUBCTRL_BASE + 0x3524)
/* USBPHY references clk frequency select */
#define IO_SUBCTRL_SC_USBPHY_FSEL_REG                   (IO_SUBCTRL_BASE + 0x3530)
#define IO_SUBCTRL_SC_USBPHY_UTMI_DATABUS_REG           (IO_SUBCTRL_BASE + 0x3538)
#define IO_SUBCTRL_SC_USBPHY_CFG_OVRD_EN_REG            (IO_SUBCTRL_BASE + 0x353C)
#define IO_SUBCTRL_SC_USBPHY_MISC_CTRL0_REG             (IO_SUBCTRL_BASE + 0x3540)
#define IO_SUBCTRL_SC_USBPHY_MISC_CTRL1_REG             (IO_SUBCTRL_BASE + 0x3544)
#define IO_SUBCTRL_SC_USBPHY_MISC_CTRL2_REG             (IO_SUBCTRL_BASE + 0x3548)
#define IO_SUBCTRL_SC_USBPHY_MISC_CTRL3_REG             (IO_SUBCTRL_BASE + 0x354C)
#define IO_SUBCTRL_SC_USBPHY_MISC_CTRL4_REG             (IO_SUBCTRL_BASE + 0x3550)
#define IO_SUBCTRL_SC_USBPHY_MISC_CTRL5_REG             (IO_SUBCTRL_BASE + 0x3554)
#define IO_SUBCTRL_SC_USBPHY_MISC_CTRL6_REG             (IO_SUBCTRL_BASE + 0x3558)
#define IO_SUBCTRL_SC_USBPHY_MISC_CTRL7_REG             (IO_SUBCTRL_BASE + 0x355C)
#define IO_SUBCTRL_SC_USBPHY_MISC_CTRL8_REG             (IO_SUBCTRL_BASE + 0x3560)
#define IO_SUBCTRL_SC_USBPHY_MISC_CTRL9_REG             (IO_SUBCTRL_BASE + 0x3564)
#define IO_SUBCTRL_SC_USBPHY_MISC_CTRL10_REG            (IO_SUBCTRL_BASE + 0x3568)
#define IO_SUBCTRL_SC_USBPHY_MISC_CTRL11_REG            (IO_SUBCTRL_BASE + 0x356C)
#define IO_SUBCTRL_SC_USBPHY_MISC_CTRL12_REG            (IO_SUBCTRL_BASE + 0x3570)
#define IO_SUBCTRL_SC_USBPHY_MISC_CTRL13_REG            (IO_SUBCTRL_BASE + 0x3574)
#define IO_SUBCTRL_SC_USBPHY_MISC_CTRL14_REG            (IO_SUBCTRL_BASE + 0x3578)
#define IO_SUBCTRL_SC_USBPHY_MISC_CTRL15_REG            (IO_SUBCTRL_BASE + 0x357C)
#define IO_SUBCTRL_SC_USBPHY_MISC_CTRL16_REG            (IO_SUBCTRL_BASE + 0x3580)
#define IO_SUBCTRL_SC_USBPHY_MISC_CTRL17_REG            (IO_SUBCTRL_BASE + 0x3584)
#define IO_SUBCTRL_SC_USB0_ARUSER_CTRL0_REG             (IO_SUBCTRL_BASE + 0x3600)
#define IO_SUBCTRL_SC_USB0_ARUSER_CTRL1_REG             (IO_SUBCTRL_BASE + 0x3604)
#define IO_SUBCTRL_SC_USB0_ARUSER_CTRL2_REG             (IO_SUBCTRL_BASE + 0x3608)
#define IO_SUBCTRL_SC_USB0_ARUSER_CTRL3_REG             (IO_SUBCTRL_BASE + 0x360C)
#define IO_SUBCTRL_SC_USB0_AWUSER_CTRL0_REG             (IO_SUBCTRL_BASE + 0x3610)
#define IO_SUBCTRL_SC_USB0_AWUSER_CTRL1_REG             (IO_SUBCTRL_BASE + 0x3614)
#define IO_SUBCTRL_SC_USB0_AWUSER_CTRL2_REG             (IO_SUBCTRL_BASE + 0x3618)
#define IO_SUBCTRL_SC_USB0_AWUSER_CTRL3_REG             (IO_SUBCTRL_BASE + 0x361C)
#define IO_SUBCTRL_SC_USB1_ARUSER_CTRL0_REG             (IO_SUBCTRL_BASE + 0x3620)
#define IO_SUBCTRL_SC_USB1_ARUSER_CTRL1_REG             (IO_SUBCTRL_BASE + 0x3624)
#define IO_SUBCTRL_SC_USB1_ARUSER_CTRL2_REG             (IO_SUBCTRL_BASE + 0x3628)
#define IO_SUBCTRL_SC_USB1_ARUSER_CTRL3_REG             (IO_SUBCTRL_BASE + 0x362C)
#define IO_SUBCTRL_SC_USB1_AWUSER_CTRL0_REG             (IO_SUBCTRL_BASE + 0x3630)
#define IO_SUBCTRL_SC_USB1_AWUSER_CTRL1_REG             (IO_SUBCTRL_BASE + 0x3634)
#define IO_SUBCTRL_SC_USB1_AWUSER_CTRL2_REG             (IO_SUBCTRL_BASE + 0x3638)
#define IO_SUBCTRL_SC_USB1_AWUSER_CTRL3_REG             (IO_SUBCTRL_BASE + 0x363C)
#define IO_SUBCTRL_SC_USB2_ARUSER_CTRL1_REG             (IO_SUBCTRL_BASE + 0x3644)
#define IO_SUBCTRL_SC_USB2_ARUSER_CTRL2_REG             (IO_SUBCTRL_BASE + 0x3648)
#define IO_SUBCTRL_SC_USB2_ARUSER_CTRL3_REG             (IO_SUBCTRL_BASE + 0x364C)
#define IO_SUBCTRL_SC_USB2_AWUSER_CTRL0_REG             (IO_SUBCTRL_BASE + 0x3650)
#define IO_SUBCTRL_SC_USB2_AWUSER_CTRL1_REG             (IO_SUBCTRL_BASE + 0x3654)
#define IO_SUBCTRL_SC_USB2_AWUSER_CTRL2_REG             (IO_SUBCTRL_BASE + 0x3658)
#define IO_SUBCTRL_SC_USB2_AWUSER_CTRL3_REG             (IO_SUBCTRL_BASE + 0x365C)
#define IO_SUBCTRL_SC_USB3_ARUSER_CTRL0_REG             (IO_SUBCTRL_BASE + 0x3660)
#define IO_SUBCTRL_SC_USB3_ARUSER_CTRL1_REG             (IO_SUBCTRL_BASE + 0x3664)
#define IO_SUBCTRL_SC_USB3_ARUSER_CTRL2_REG             (IO_SUBCTRL_BASE + 0x3668)
#define IO_SUBCTRL_SC_USB3_ARUSER_CTRL3_REG             (IO_SUBCTRL_BASE + 0x366C)
#define IO_SUBCTRL_SC_USB3_AWUSER_CTRL0_REG             (IO_SUBCTRL_BASE + 0x3670)
#define IO_SUBCTRL_SC_USB3_AWUSER_CTRL1_REG             (IO_SUBCTRL_BASE + 0x3674)
#define IO_SUBCTRL_SC_USB3_AWUSER_CTRL2_REG             (IO_SUBCTRL_BASE + 0x3678)
#define IO_SUBCTRL_SC_USB3_AWUSER_CTRL3_REG             (IO_SUBCTRL_BASE + 0x367C)
#define IO_SUBCTRL_SC_USB_BRG_CTRL_REG                  (IO_SUBCTRL_BASE + 0x3680)
#define IO_SUBCTRL_SC_USB_POWERPRESENT_CTRL_REG         (IO_SUBCTRL_BASE + 0x3684)
#define IO_SUBCTRL_SC_USB_VBUSVALID_CTRL_REG            (IO_SUBCTRL_BASE + 0x3688)
#define IO_SUBCTRL_SC_USB_POWER_EN_CTRL_REG             (IO_SUBCTRL_BASE + 0x368C)
#define IO_SUBCTRL_SC_USB_PORT_OCA_CTRL_REG             (IO_SUBCTRL_BASE + 0x3690)
#define IO_SUBCTRL_SC_USB_PROBE_SEL_REG                 (IO_SUBCTRL_BASE + 0x3694)
#define IO_SUBCTRL_SC_PCIE_AXPROT_CTRL_REG              (IO_SUBCTRL_BASE + 0x36A0)
#define IO_SUBCTRL_SC_NIC_AXPROT_CTRL_REG               (IO_SUBCTRL_BASE + 0x36A4)
#define IO_SUBCTRL_SC_USBC0_AHB_MATRIX_REG              (IO_SUBCTRL_BASE + 0x36A8)
#define IO_SUBCTRL_SC_DBG_HADDR_USBC0_REG               (IO_SUBCTRL_BASE + 0x36AC)
#define IO_SUBCTRL_SC_DBG_HWDATA_USBC0_REG              (IO_SUBCTRL_BASE + 0x36B0)
#define IO_SUBCTRL_SC_DBG_HRDATA_USBC0_REG              (IO_SUBCTRL_BASE + 0x36B4)
#define IO_SUBCTRL_SC_DBG_MISC_USBC0_REG                (IO_SUBCTRL_BASE + 0x36B8)
#define IO_SUBCTRL_SC_USBC1_AHB_MATRIX_REG              (IO_SUBCTRL_BASE + 0x36BC)
#define IO_SUBCTRL_SC_DBG_HADDR_USBC1_REG               (IO_SUBCTRL_BASE + 0x36C0)
#define IO_SUBCTRL_SC_DBG_HWDATA_USBC1_REG              (IO_SUBCTRL_BASE + 0x36C4)
#define IO_SUBCTRL_SC_DBG_HRDATA_USBC1_REG              (IO_SUBCTRL_BASE + 0x36C8)
#define IO_SUBCTRL_SC_DBG_MISC_USBC1_REG                (IO_SUBCTRL_BASE + 0x36CC)
#define IO_SUBCTRL_SC_USBC2_AHB_MATRIX_REG              (IO_SUBCTRL_BASE + 0x36D0)
#define IO_SUBCTRL_SC_DBG_HADDR_USBC2_REG               (IO_SUBCTRL_BASE + 0x36D4)
#define IO_SUBCTRL_SC_DBG_HWDATA_USBC2_REG              (IO_SUBCTRL_BASE + 0x36D8)
#define IO_SUBCTRL_SC_DBG_HRDATA_USBC2_REG              (IO_SUBCTRL_BASE + 0x36DC)
#define IO_SUBCTRL_SC_DBG_MISC_USBC2_REG                (IO_SUBCTRL_BASE + 0x36E0)
#define IO_SUBCTRL_SC_USBC3_AHB_MATRIX_REG              (IO_SUBCTRL_BASE + 0x36E4)
#define IO_SUBCTRL_SC_DBG_HADDR_USBC3_REG               (IO_SUBCTRL_BASE + 0x36E8)
#define IO_SUBCTRL_SC_DBG_HWDATA_USBC3_REG              (IO_SUBCTRL_BASE + 0x36EC)
#define IO_SUBCTRL_SC_DBG_HRDATA_USBC3_REG              (IO_SUBCTRL_BASE + 0x36F0)
#define IO_SUBCTRL_SC_DBG_MISC_USBC3_REG                (IO_SUBCTRL_BASE + 0x36F4)
#define IO_SUBCTRL_SC_NIC_CLK_SEL_REG                   (IO_SUBCTRL_BASE + 0x3700)
#define IO_SUBCTRL_SC_NIC_TX_MODE_REG                   (IO_SUBCTRL_BASE + 0x3704)
#define IO_SUBCTRL_SC_INI_INJ_EN_REG                    (IO_SUBCTRL_BASE + 0x3708)
#define IO_SUBCTRL_SC_NIC_CMD_TYPE_REG                  (IO_SUBCTRL_BASE + 0x370C)
#define IO_SUBCTRL_SC_HILINK_GE_LOS_SEL_REG             (IO_SUBCTRL_BASE + 0x3710)
#define IO_SUBCTRL_SC_HILINK_USB_GE_DIV_MODE_REG        (IO_SUBCTRL_BASE + 0x3714)
#define IO_SUBCTRL_SC_EPHY_RST_CTRL_REG                 (IO_SUBCTRL_BASE + 0x3718)
#define IO_SUBCTRL_SC_TSENSOR_INT_REG                   (IO_SUBCTRL_BASE + 0x4000)
#define IO_SUBCTRL_SC_TSENSOR_INT_MASK_REG              (IO_SUBCTRL_BASE + 0x4004)
#define IO_SUBCTRL_SC_OOO_ECC_INTMASK_0_REG             (IO_SUBCTRL_BASE + 0x4100)
#define IO_SUBCTRL_SC_OOO_ECC_RAWINT_0_REG              (IO_SUBCTRL_BASE + 0x4104)
#define IO_SUBCTRL_SC_OOO_ECC_INTSTAT_0_REG             (IO_SUBCTRL_BASE + 0x4108)
#define IO_SUBCTRL_SC_OOO_ECC_INTMASK_1_REG             (IO_SUBCTRL_BASE + 0x410C)
#define IO_SUBCTRL_SC_OOO_ECC_RAWINT_1_REG              (IO_SUBCTRL_BASE + 0x4110)
#define IO_SUBCTRL_SC_OOO_ECC_INTSTAT_1_REG             (IO_SUBCTRL_BASE + 0x4114)
#define IO_SUBCTRL_SC_SMMU_ICG_ST_REG                   (IO_SUBCTRL_BASE + 0x5300)
#define IO_SUBCTRL_SC_GPIO_ICG_ST_REG                   (IO_SUBCTRL_BASE + 0x5308)
#define IO_SUBCTRL_SC_APB_IO_MUX_ICG_ST_REG             (IO_SUBCTRL_BASE + 0x5310)
#define IO_SUBCTRL_SC_PROBE_ICG_ST_REG                  (IO_SUBCTRL_BASE + 0x5318)
#define IO_SUBCTRL_SC_MDIO_ICG_ST_REG                   (IO_SUBCTRL_BASE + 0x5320)
#define IO_SUBCTRL_SC_HILINK0_ICG_ST_REG                (IO_SUBCTRL_BASE + 0x5328)
#define IO_SUBCTRL_SC_HILINK1_ICG_ST_REG                (IO_SUBCTRL_BASE + 0x5330)
#define IO_SUBCTRL_SC_SDS_ICG_ST_REG                    (IO_SUBCTRL_BASE + 0x5338)
#define IO_SUBCTRL_SC_PCIE_BRG_ICG_ST_REG               (IO_SUBCTRL_BASE + 0x5340)
#define IO_SUBCTRL_SC_PCIE0_CTRL0_ICG_ST_REG            (IO_SUBCTRL_BASE + 0x5348)
#define IO_SUBCTRL_SC_PCIE0_CTRL1_ICG_ST_REG            (IO_SUBCTRL_BASE + 0x5350)
#define IO_SUBCTRL_SC_PCIE1_CTRL0_ICG_ST_REG            (IO_SUBCTRL_BASE + 0x5358)
#define IO_SUBCTRL_SC_PCIE1_CTRL1_ICG_ST_REG            (IO_SUBCTRL_BASE + 0x5360)
#define IO_SUBCTRL_SC_PCIE2_CTRL0_ICG_ST_REG            (IO_SUBCTRL_BASE + 0x5368)
#define IO_SUBCTRL_SC_PCIE2_CTRL1_ICG_ST_REG            (IO_SUBCTRL_BASE + 0x5370)
#define IO_SUBCTRL_SC_PCIE3_CTRL0_ICG_ST_REG            (IO_SUBCTRL_BASE + 0x5378)
#define IO_SUBCTRL_SC_PCIE3_CTRL1_ICG_ST_REG            (IO_SUBCTRL_BASE + 0x5380)
#define IO_SUBCTRL_SC_USB_ICG_ST_REG                    (IO_SUBCTRL_BASE + 0x5388)
#define IO_SUBCTRL_SC_SATA_ICG_ST_REG                   (IO_SUBCTRL_BASE + 0x5390)
#define IO_SUBCTRL_SC_NIC_INTF0_ICG_ST_REG              (IO_SUBCTRL_BASE + 0x5398)
#define IO_SUBCTRL_SC_NIC_INTF1_ICG_ST_REG              (IO_SUBCTRL_BASE + 0x53A0)
#define IO_SUBCTRL_SC_RGMII_ICG_ST_REG                  (IO_SUBCTRL_BASE + 0x53A8)
#define IO_SUBCTRL_SC_HPM_CLK_ST_REG                    (IO_SUBCTRL_BASE + 0x53B0)
#define IO_SUBCTRL_SC_TSENSOR_ICG_ST_REG                (IO_SUBCTRL_BASE + 0x53C0)
#define IO_SUBCTRL_SC_HILINK_SRAM_ICG_ST_REG            (IO_SUBCTRL_BASE + 0x53C8)
#define IO_SUBCTRL_SC_BCBIST_ICG_ST_REG                 (IO_SUBCTRL_BASE + 0x53D0)
#define IO_SUBCTRL_SC_GPIO_RESET_ST_REG                 (IO_SUBCTRL_BASE + 0x5400)
#define IO_SUBCTRL_SC_APB_IO_MUX_RESET_ST_REG           (IO_SUBCTRL_BASE + 0x5408)
#define IO_SUBCTRL_SC_MDIO_RESET_ST_REG                 (IO_SUBCTRL_BASE + 0x5418)
#define IO_SUBCTRL_SC_HILINK0_RESET_ST_REG              (IO_SUBCTRL_BASE + 0x5420)
#define IO_SUBCTRL_SC_HILINK1_RESET_ST_REG              (IO_SUBCTRL_BASE + 0x5428)
#define IO_SUBCTRL_SC_SDS_RESET_ST_REG                  (IO_SUBCTRL_BASE + 0x5430)
#define IO_SUBCTRL_SC_USB_RESET_ST_REG                  (IO_SUBCTRL_BASE + 0x5438)
#define IO_SUBCTRL_SC_USBPHY_RESET_ST_REG               (IO_SUBCTRL_BASE + 0x5440)
#define IO_SUBCTRL_SC_SATA_RESET_ST_REG                 (IO_SUBCTRL_BASE + 0x5448)
#define IO_SUBCTRL_SC_NIC_INTF0_RESET_ST_REG            (IO_SUBCTRL_BASE + 0x5450)
#define IO_SUBCTRL_SC_NIC_INTF1_RESET_ST_REG            (IO_SUBCTRL_BASE + 0x5458)
#define IO_SUBCTRL_SC_PCIE0_CTRL_RESET_ST_REG           (IO_SUBCTRL_BASE + 0x5460)
#define IO_SUBCTRL_SC_PCIE1_CTRL_RESET_ST_REG           (IO_SUBCTRL_BASE + 0x5468)
#define IO_SUBCTRL_SC_PCIE2_CTRL_RESET_ST_REG           (IO_SUBCTRL_BASE + 0x5470)
#define IO_SUBCTRL_SC_PCIE3_CTRL_RESET_ST_REG           (IO_SUBCTRL_BASE + 0x5478)
#define IO_SUBCTRL_SC_RGMII_RESET_ST_REG                (IO_SUBCTRL_BASE + 0x5480)
#define IO_SUBCTRL_SC_HPM_RESET_ST_REG                  (IO_SUBCTRL_BASE + 0x5488)
#define IO_SUBCTRL_SC_TSENSOR_RESET_ST_REG              (IO_SUBCTRL_BASE + 0x54C0)
#define IO_SUBCTRL_SC_BCBIST_RESET_ST_REG               (IO_SUBCTRL_BASE + 0x54C8)
#define IO_SUBCTRL_SC_USB3_STATE_REG                    (IO_SUBCTRL_BASE + 0x6000)
#define IO_SUBCTRL_SC_USB_LOWER_POWER_REG               (IO_SUBCTRL_BASE + 0x6004)
#define IO_SUBCTRL_SC_USB_BRG_ST_REG                    (IO_SUBCTRL_BASE + 0x6008)
#define IO_SUBCTRL_SC_USBPHY_ST_REG                     (IO_SUBCTRL_BASE + 0x600C) /* USBPHY STATUS */
#define IO_SUBCTRL_SC_USB0_RAM0_ECC_ST_REG              (IO_SUBCTRL_BASE + 0x6010) /* USB0 RAM0 ECC STATUS */
#define IO_SUBCTRL_SC_USB0_RAM1_ECC_ST_REG              (IO_SUBCTRL_BASE + 0x6014) /* USB0 RAM1 ECC STATUS */
#define IO_SUBCTRL_SC_USB0_RAM2_ECC_ST_REG              (IO_SUBCTRL_BASE + 0x6018) /* USB0 RAM2 ECC STATUS */
#define IO_SUBCTRL_SC_USB0_RAM3_ECC_ST_REG              (IO_SUBCTRL_BASE + 0x601C) /* USB0 RAM3 ECC STATUS */
#define IO_SUBCTRL_SC_USB0_RAM4_ECC_ST_REG              (IO_SUBCTRL_BASE + 0x6020) /* USB0 RAM4 ECC STATUS */
#define IO_SUBCTRL_SC_USB1_RAM0_ECC_ST_REG              (IO_SUBCTRL_BASE + 0x6024) /* USB1 RAM0 ECC STATUS */
#define IO_SUBCTRL_SC_USB1_RAM1_ECC_ST_REG              (IO_SUBCTRL_BASE + 0x6028) /* USB1 RAM1 ECC STATUS */
#define IO_SUBCTRL_SC_USB1_RAM2_ECC_ST_REG              (IO_SUBCTRL_BASE + 0x602C) /* USB1 RAM2 ECC STATUS */
#define IO_SUBCTRL_SC_USB1_RAM3_ECC_ST_REG              (IO_SUBCTRL_BASE + 0x6030) /* USB1 RAM3 ECC STATUS */
#define IO_SUBCTRL_SC_USB1_RAM4_ECC_ST_REG              (IO_SUBCTRL_BASE + 0x6034) /* USB1 RAM4 ECC STATUS */
#define IO_SUBCTRL_SC_USB2_RAM0_ECC_ST_REG              (IO_SUBCTRL_BASE + 0x6038) /* USB2 RAM0 ECC STATUS */
#define IO_SUBCTRL_SC_USB2_RAM1_ECC_ST_REG              (IO_SUBCTRL_BASE + 0x603C) /* USB2 RAM1 ECC STATUS */
#define IO_SUBCTRL_SC_USB2_RAM2_ECC_ST_REG              (IO_SUBCTRL_BASE + 0x6040) /* USB2 RAM2 ECC STATUS */
#define IO_SUBCTRL_SC_USB2_RAM3_ECC_ST_REG              (IO_SUBCTRL_BASE + 0x6044) /* USB2 RAM3 ECC STATUS */
#define IO_SUBCTRL_SC_USB2_RAM4_ECC_ST_REG              (IO_SUBCTRL_BASE + 0x6048) /* USB2 RAM4 ECC STATUS */
#define IO_SUBCTRL_SC_USB3_RAM0_ECC_ST_REG              (IO_SUBCTRL_BASE + 0x604C) /* USB3 RAM0 ECC STATUS */
#define IO_SUBCTRL_SC_USB3_RAM1_ECC_ST_REG              (IO_SUBCTRL_BASE + 0x6050) /* USB3 RAM1 ECC STATUS */
#define IO_SUBCTRL_SC_USB3_RAM2_ECC_ST_REG              (IO_SUBCTRL_BASE + 0x6054) /* USB3 RAM2 ECC STATUS */
#define IO_SUBCTRL_SC_USB3_RAM3_ECC_ST_REG              (IO_SUBCTRL_BASE + 0x6058) /* USB3 RAM3 ECC STATUS */
#define IO_SUBCTRL_SC_USB3_RAM4_ECC_ST_REG              (IO_SUBCTRL_BASE + 0x605C) /* USB3 RAM4 ECC STATUS */
#define IO_SUBCTRL_SC_TSENSOR_ST_REG                    (IO_SUBCTRL_BASE + 0x6100) /* tsensor STATUS */
#define IO_SUBCTRL_SC_DCIP_BCBIST_ST_REG                (IO_SUBCTRL_BASE + 0x6200) /* DCIP STATUS */
#define IO_SUBCTRL_SC_TSENSOR_TIMEOUT_STATUS_REG        (IO_SUBCTRL_BASE + 0x8010) /* TSENSOR IRQ STATUS */
#define IO_SUBCTRL_SC_SYSCTRL_LOCK_REG                  (IO_SUBCTRL_BASE + 0xF100) /* Safty access */
#define IO_SUBCTRL_SC_SYSCTRL_UNLOCK_REG                (IO_SUBCTRL_BASE + 0xF110) /* Safty access */
#define IO_SUBCTRL_SC_IOMUX_TZPC0_REG                   (IO_SUBCTRL_BASE + 0xF114)
#define IO_SUBCTRL_SC_IOMUX_TZPC1_REG                   (IO_SUBCTRL_BASE + 0xF118)
#define IO_SUBCTRL_SC_PROBE_MUX_SEL_REG                 (IO_SUBCTRL_BASE + 0xF200)
/* SMMU_ICG_EN_SRST_REQ safty properties switch */
#define IO_SUBCTRL_SC_SMMU_ICG_EN_SRST_REQ_SWITCHER_REG (IO_SUBCTRL_BASE + 0xF300)
#define IO_SUBCTRL_SC_ECO_RSV0_REG                      (IO_SUBCTRL_BASE + 0xFF00) /* ECO RW0 */
#define IO_SUBCTRL_SC_ECO_RSV1_REG                      (IO_SUBCTRL_BASE + 0xFF04) /* ECO RW1 */
#define IO_SUBCTRL_SC_ECO_RSV2_REG                      (IO_SUBCTRL_BASE + 0xFF08) /* ECO RW2 */
#define IO_SUBCTRL_SC_ECO_RSV3_REG                      (IO_SUBCTRL_BASE + 0xFF0C) /* ECO RW3 */
#define IO_SUBCTRL_SC_ECO_RSV4_REG                      (IO_SUBCTRL_BASE + 0xFF10) /* ECO RO4 */
#define IO_SUBCTRL_SC_ECO_RSV5_REG                      (IO_SUBCTRL_BASE + 0xFF14) /* ECO RO5 */
#define IO_SUBCTRL_SC_VER_NUM_REG                       (IO_SUBCTRL_BASE + 0xFFFC)

#endif // __IO_SUBCTRL_REG_OFFSET_H__
